Z80 FPGA Versions Save

• TinyBasic Basic interpreter added (not fully working yet)
• ZEXDOC test added. 62/67 Test passed

• Verilog files embedded into icestudio blocks. No more dependency on .v external files
• TX/RX UART for serial communication mapped in ports 0x10 and 0x11
• Input port 0x00. The sw2 pushbutton can be read
• Examples of using the uart and the pushbutton

• 16KB memory, mapped from 0x0000 to 0x4000
• Hardware Bootloader: the firmaware can be uploaded into the memory from the PC through serial port
• More examples added
• Preliminary tests with a memory mapped uart and one input button

• Same components than version 1.0.0 : 8KB RAM, 8KB ROM, 1 output port connected to LEDs
• Changed to positive logic: z80 signals, chip selects, etc
• Chip select logic embedded into their own blocks
• Labels in different colors
• Improved the documentation of the design
• Memory blocks pins reorganized

Initial Release

• 8KB ROM (0x0000 - 0x1FFF)
• 8KB RAM (location: 0x8000)
• 1 Output port (0x40) connected to 8 LEDs
• Tested on the Alhambra-II FPGA board